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ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 256mb e-die ddr 400 sdram specification revision 1.1 60ball fbga (x4/x8)
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 256mb e-die revision history revision 1.0 (july, 2003) - first release revision 1.1 (september, 2003) - modified ddr sdram spec items & test conditions
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 ? 200mhz clock, 400mbps data rate. ? vdd= +2.6v + 0.10v, vddq= +2.6v + 0.10v ? double-data-rate arch itecture; two data transfers per clock cycle ? bidirectional data strobe [dq] (x4,x8) ? four banks operation ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? mrs cycle with address key programs -. read latency 3 (clock) for ddr400 , 2.5 (clock) for ddr333 -. burst length (2, 4, 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive go ing edge of the system clock(ck) ? data i/o transactions on both edges of data strobe ? edge aligned data output, center aligned data input ? dm for write masking only (x4, x8) ? auto & self refresh ? 7.8us refresh interv al(8k/64ms refresh) ? maximum burst refresh cycle : 8 ? 60ball fbga package key features ordering information part no. org. max freq. interface package k4h560438e-gccc 64m x 4 cc(ddr400@cl=3) sstl2 60 fbga k4h560438e-gcc4 c4(ddr400@cl=3) K4H560838E-GCCC 32m x 8 cc(ddr400@cl=3) sstl2 60 fbga k4h560838e-gcc4 c4(ddr400@cl=3) *cl : cas latency operating frequencies - cc(ddr400@cl=3) - c4(ddr400@cl=3) speed @cl3 200mhz 200mhz cl-trcd-trp 3 - 3 - 3 3 - 4 - 4
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 ball description dm is internally loaded to match dq and dqs identically. row & column address configuration organization row address column address 64mx4 a0~a12 a0-a9, a11 32mx8 a0~a12 a0-a9 1 vssq nc nc nc nc vref 2 nc vddq vssq vddq vssq vss ck a12 a11 a8 a6 a4 3 vss dq3 nc dq2 dqs dm ck cke a9 a7 a5 vss abcdefghjklm 7 vdd dq0 nc dq1 nc nc we ras ba1 a0 a2 vdd 8 nc vssq vddq vssq vddq vdd cas cs ba0 a10/ap a1 a3 9 vddq nc nc nc nc nc 1 vssq nc nc nc nc vref 2 dq7 vddq vssq vddq vssq vss ck a12 a11 a8 a6 a4 3 vss dq6 dq5 dq4 dqs dm ck cke a9 a7 a5 vss abcdefghjklm 7 vdd dq1 dq2 dq3 nc nc we ras ba1 a0 a2 vdd 8 dq0 vssq vddq vssq vddq vdd cas cs ba0 a10/ap a1 a3 9 vddq nc nc nc nc nc 32m x 8bit 64m x 4bit ( bottom view )
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 60ball fbga package dimension package physical dimension ( unit : mm ) (0.90) (0.90) 8.0 0 0.10 14.00 0.10 14.0 0.10 0.10 max 0.45 0.05 0.35 0.05 1.10 0.10 1 2 3 4 5 6 7 8 9 encapsulant area 8.00 0.10 0.80 x 4 = 3.20 1.60 1.60 a b c d e f g h j k l m 0.80 0.50 5.50 1.00 x 11 = 11.00 14.00 0.10 5.50 60 - 0.45 0.05 0.80 x 8 = 6.40 top view bottom view (1.80) 0.50 1.00
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 8mx8/ 4mx16 8mx8/ 4mx16 8mx8/ 4mx16 8mx8/ 4mx16 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register dll strobe gen. ck, ck add lcke ck, ck cke cs ras cas we ck, ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck x8/16 x8/16 x4/8 x4/8 lwe ldm (x4x8) x4/8 dqi data strobe block diagram (64mbit x 4 / 32mbit x 8 i/o x 4 banks) ldm (x4x8) dm input register
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 symbol type description ck, ck input clock : ck and ck are differential clock inputs. all address and control input signals are sam- pled on the positive edge of ck and negative edge of ck . output (read) data is referenced to both edges of ck. internal clock signals are derived from ck/ck . cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. de activating the clock provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions except for disabling outputs, which is achieved asynchronously . input buffers, excluding ck, ck and cke are disabled dur- ing power-down and self refresh modes, providing low standby power. cke will recognize an lvcmos low level prior to vref being stable on power-up. cs input chip select : cs enables(registered low) and disabl es(registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input command inputs : ras , cas and we (along with cs ) define the command being entered. dm input input data mask : dm is an input mask signal for write data. input dat a is masked when dm is sampled high along with that input data dur ing a write access. dm is sampled on both edges of dqs. although dm pins are input onl y, the dm loading matches the dq and dqs loading. dm may be driven high, low, or floating during reads. ba0, ba1 input bank addres inputs : ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a [0 : 12] input address inputs : provide the row address fo r active commands, and the column address and auto precharge bit for read/write commands , to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to deter- mine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code during a mode regist er set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). dq i/o data input/output : data bus dqs i/o data strobe : output with read data, input wi th write data. edge-aligned with read data, cen- tered in write data. used to capture write data. nc - no connect : no internal el ectrical connection is present. vddq supply dq power supply : +2.6v 0.1v. vssq supply dq ground. vdd supply power supply : +2.6v 0.1v (device specific). vss supply ground. vref input sstl_2 reference voltage. input/output function description
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9, a11,a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll l h x 3 self refresh entry l 3 exit l h lh h h x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv v v exit l h x x x x precharge power down mode entry h l hx x x x lh h h exit l h hx x x lv v v dm(udm/ldm for x16 only) h x x 8 no operation (nop) : not defined h x hx x x x 9 lh h h 9 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/mrs can be issued onl y at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are sa me as the cbr refresh of dram. the automatical precharge without ro w precharge command is meant by "auto". auto/self refresh can be iss ued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, writ e, row active and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row acti ve and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row ac tive and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row ac tive and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm(x4/8) sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0) . dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. note :
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 16m x 4bit x 4 banks / 8m x 8bit x 4 banks banks double data rate sdram the k4h560438e / k4h560838e / is 268,435,456 bits of double dat a rate synchronous dram organized as 4x 16,785,216 / 4x 8,388,608 words by 4/ 8bits, fabricated with samsung s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 333mb/s per pin. i/o trans actions are possible on both edges of dqs. range of operating fre- quencies, programmable burst length and program mable latencies allow the device to be us eful for a variety of high performance mem- ory system applications. general description absolute maximum rating parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd & v ddq supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 w short circuit current i os 50 ma note : permanent device damage may occur if ab solute maximum ra tings are exceeded. functional operation should be restri cted to recommend operation condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. dc operating conditions recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.5 2.7 i/o supply voltage v ddq 2.5 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 1.vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on vref ma y not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the diff erence between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is specified for the same temperat ure and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. fo r a given output, it represents t he maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to s ource voltages from 0.1 to 1.0. note :
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 input/output capacitance (v dd =2.6, v ddq =2.6v, t a = 25 c, f=1mhz) parameter symbol min max delta unit note input capacitance (a0 ~ a12, ba0 ~ ba1, cke, cs , ras ,cas , we ) cin1 1.5 2.5 0.5 pf 4 input capacitance( ck, ck ) cin2 1.5 2.5 0.25 pf 4 data & dqs input/output capacitance cout 3.5 4.5 0.5 pf 1,2,3,4 input capacitance (dm) cin3 3.5 4.5 pf 1,2,3,4 note : 1.these values are guaranteed by design and are tested on a sample basis only. 2. although dm is an input -only pi n, the input capacitance of this pin must model the input capacitance of the dq and dqs pin s. this is required to match signal propagation times of dq, dqs, and dm in the system. 3. unused pins are tied to ground. 4. this parameteer is sampled. vddq = +2.6v +0.1v, vdd = +2.6v +0.1v, f=100mhz, ta=25 c, vout(dc) = vddq/2, vout(peak to peak) = 0.2v. dm inputs are grouped with i/o pins - reflecti ng the fact that they are matched in loadi ng (to facilitate trace matching at the board level). ddr sdram spec items & test conditions conditions symbol operating current - one bank active-precharge; trc=trcmin; tck=5ns for dd r400; dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; cs = high between valid commands. idd0 operating current - on e bank operation ; one bank open, bl=4, reads - refer to the following page for detailed test condition; cs = high between valid commands. idd1 percharge power-down standby current; all banks idle; power - down mode; cke = =vih(min);all banks idle; cke > = vih(min); tck=5ns for ddr400; address and other control inputs changing once per clock cycle; vin = vref for dq,dqs and dm idd2f precharge quiet standby current; cs# > = vih(min); all banks idle; cke > = vih(min); tck=5ns for ddr 400; address and other control inputs st able at >= vih(min) or == vih(min); cke>=vih(min); one bank active; active - precharge; trc=trasmax; tck=5ns fo r ddr400; dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle idd3n operating current - burst read; burst length = 2; reads; continguous burst ; one bank active; address and control inputs changing once per clock cycle; cl=3 at 5ns for ddr400; 50% of data changing on every transfer; lout = 0 m a idd4r operating current - burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; cl=3 at tc k=5ns for ddr400; dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every transfer idd4w auto refresh current; trc = trfc(min) - 14*tck for ddr400 at tck=5ns; idd5 self refresh current; cke =< 0.2v; external cl ock on; tck = 5ns for ddr400. idd6
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 ddr sdram i dd spec table (v dd =2.7v, t = 10 c) symbol 64mx4 (k4h560438e), 32mx8 (k4h560838e) unit notes cc(ddr400@cl=3) c4(ddr400@cl=3) idd0 105 100 ma idd1 130 130 ma idd2p 44 ma idd2f 30 30 ma idd2q 25 25 ma idd3p 55 55 ma idd3n 75 75 ma idd4r 185 185 ma idd4w 190 190 ma idd5 180 180 ma idd6 normal 33 ma low power 1.5 1.5 ma optional idd7a 310 290 ma < detailed test conditions for ddr sdram idd1 & idd7a > idd1 : operating curre nt: one bank operation 1. only one bank is accessed with trc(mi n), burst mode, address and control inputs change logic state once per deselect cycle. iout = 0ma 2. timing patterns - cc/c4(200mhz,cl=3) : tc k=5ns, cl=3, bl=4, trcd=3*tck(cc) 4*tck(c4 ), trc=11*tck(cc) 12*tck(c4), tras=8*tck setup : a0 n n r0 n n n n p0 n n read : a0 n n r0 n n n n p0 n n - repeat the same timing with random address changing *50% of data changing at every transfer idd7a : operating current: four bank operation 1. four banks are being interleaved with trc(min), burst m ode, address and control inputs on deselet edge are not changing. iout = 1ma 2. timing patterns - cc/c4(200mhz,cl=3) : tc k=5ns, cl=3, bl=4, trcd=3*tck(cc) 4*tck(c4 ), trc=11*tck(cc) 12*tck(c4), tras=8*tck setup : a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n n read : a0 n a1 ra0 a2 ra1 a3 ra2 n ra3 n n - repeat the same timing with random address changing *50% of data changing at every transfer legend : a = activate, r=read, w=write, p=precharge, n=nop
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 ac operating conditions parameter/condition symbol min max-10 unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v input differential voltage, ck and /ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and /ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 0.6875 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.3125 6.5 7.0 vdd overshoot maximum amplitude = 1.5v area = 4.5v-ns maximum amplitude = 1.5v undershoot gnd volts (v) tims(ns) ac overshoot/undershoot definition notes : 1. vid is the magnitude of the difference between the input le vel on ck and the input level on /ck. 2. the value of vix is expected to equal 0. 5*vddq of the transmitting device and must tr ack variations in the dc level of the s ame. ac overshoot/undershoot specification for address and control pins parameter specification ddr400 maximum peak amplitude allowed for overshoot 1.5v maximum peak amplitude allowed for undershoot 1.5v the area between the overshoot signal and vdd must be less than or equal to 4.5v-ns the area between the undershoot signal and gnd must be less than or equal to 4.5v-ns
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 5 4 3 2 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 vddq overshoot maximum amplitude = 1.2v area = 2.4v-ns maximum amplitude = 1.2v undershoot gnd volts (v) tims(ns) dq/dm/dqs ac overshoot/undershoot definition overshoot/undershoot specification for data, strobe, and mask pins parameter specification ddr400 maximum peak amplitude allo wed for overshoot 1.2v maximum peak amplitude allowed for undershoot 1.2v the area between the overshoot signal and vdd must be less than or equal to 2.5v-ns the area between the undershoot signal and gnd must be less than or equal to 2.5v-ns
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 ac timing parameters and specifications parameter symbol - cc(ddr400@cl=3) - c4(ddr400@cl=3) unit note min max min max row cycle time trc 55 60 ns refresh row cycle time trfc 70 70 ns row active time tras 40 70k 40 70k ns ras to cas delay trcd 15 18 ns row precharge time trp 15 18 ns row active to row active delay trrd 10 10 ns write recovery time twr 15 15 ns internal write to read command delay twtr 2 2 tck clock cycle time cl=3.0 tck 510510ns 16 cl=2.5 612612ns clock high level width tch 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/c k tdqsck -0.55 +0.55 -0.55 +0.55 ns output data access time from ck/ck tac -0.65 +0.65 -0.65 +0.65 ns data strobe edge to ouput data edge tdqsq - 0.4 - 0.4 ns 13 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.72 1.28 0.72 1.28 tck write preamble setup time twpres 0 0 ps 5 write preamble twpre 0.25 0.25 tck write postamble twpst 0.4 0.6 0.4 0.6 tck 4 dqs falling edge to ck rising-setup time tdss 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 tck address and control input setup time tis 0.6 0.6 ns h,7~10 address and control input hold time tih 0.6 0.6 ns h,7~10 data-out high impedence time from ck/ck thz - tac max - tac max ns 3 data-out low impedence time from ck/ck tlz tac min tac max tac min tac max ns 3 mode register set cycle time tmrd 2 2 tck dq & dm setup time to dqs, slew rate 0.5v/ns tds 0.4 0.4 ns i, j dq & dm hold time to dqs, slew rate 0.5v/ns tdh 0.4 0.4 ns i, j dq & dm input pulse width tdipw 1.75 1.75 ns 9 control & address input pulse width for each input tipw 2.2 2.2 ns 9 refresh interval time up to 128mb trefi 15.6 15.6 us 6 256mb, 512mb, 1gb 7.8 7.8 us output dqs valid window tqh thp -tqhs - thp -tqhs -ns12 clock half period thp min tch/tcl - min tch/tcl - ns 11, 12
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 component notes 1.v id is the magnitude of the diff erence between the input level on ck and the input level on ck . 2. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 3. thz and tlz transitions occur in the same access time wi ndows as valid data transitions. these parameters are not referenc ed to a specific voltage level but s pecify when the device output in no longer driving (hz), or begins driving (lz). 4. the maximum limit for this paramete r is not a device limit. the device will operat e with a greater value for this paramete r, but sys tem performance (bus turnaround) will degrade accordingly. 5. the specific require ment is that dqs be valid (high, low, or at some point on a valid transition) on or before this ck edg e. a valid transition is defined as monotonic and meeting the input slew rate spec ifications of the dev ice. when no writes we re previ ously in progress on the bus, dqs will be tran sitioning from high- z to logic low. if a previous write was in progress , dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 6. a maximum of eight auto refresh comm ands can be posted to any given ddr sdram device. 7. for command/address input slew rate 0.5 v/ns 8. for ck & ck slew rate 0.5 v/ns 9. these parameters guarantee device timing, but they are not necessarily te sted on each device. they may be guaranteed by device design or tester correlation. 10. slew rate is measur ed between voh(ac) and vol(ac). 11. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the mini mum specification limits for tc l and tch).....for example, tcl and tch are = 50% of th e period, less the half period jit ter (tjit(hp)) of the clock source, and less the half period jitter due to crosstalk (tji t(crosstalk)) into the clock traces. 12. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or clo ck low (tch, tcl). tqhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effec ts, and p- channel to n-channel variation of the output drivers. 13. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-c hannel variation of the output drivers for any given cycle. 14. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highes t integer. example: for ddr400(cc) at cl= 3 and tck=5ns tdal = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}clk tdal = 6 clocks 15. in all circumstances, txsnr can be satisfied using t xsnr=trfcmin+1*tck 16. the only time that the clock frequency is allowed to change is during self-refresh mode. parameter symbol - cc(ddr400@cl=3) - c4(ddr400@cl=3) unit note min max min max data hold skew factor tqhs 0.5 0.5 ns 12 auto precharge write recovery + precharge time tdal - - - - ns 14 exit self refresh to non-read command txsnr 75 75 ns 15 exit self refresh to read command txsrd 200 - 200 - tck
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 table 4 : input/output setup & hold de rating for rise/fall delta slew rate table 5 : output slew rate ch aracteristice (x8 devices only) table 6 : output slew rate characteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics delta slew rate tds tdh units notes +/- 0.0 v/ns 0 0 ps i +/- 0.25 v/ns +50 +50 ps i +/- 0.5 v/ns +100 +100 ps i slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g ac characteristics ddr400 parameter min max notes output slew rate matching ratio (pullup to pulldown) - - e,k system characteristics for ddr sdram the following specificat ion parameters are required in systems using ddr400 devices to ensure proper system perfor- mance. these characteristics are for system simu lation purposes and are guaranteed by design. table 1 : input slew rate for dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate ac characteristics ddr400 parameter symbol min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 v/ns a, k input slew rate tis tih units notes 0.5 v/ns 0 0 ps h 0.4 v/ns +50 0 ps h 0.3 v/ns +100 0 ps h input slew rate tds tdh units notes 0.5 v/ns 0 0 ps j 0.4 v/ns +75 +75 ps j 0.3 v/ns +150 +150 ps j
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 1. output test point vssq 50 ? figure 1 : pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2. output test point vddq 50 ? figure 2 : pulldown sl ew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is meas ured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met fo r any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are sw itching from either high to low, or low to high. for maximum slew rate, only one dq is switching from either high to low, or low to high. the remaining dq bits remain the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.6v, typical process minimum : 70 c (t ambient), vddq = 2. 5v, slow - slow process maximum : 0 c (t ambient), vddq = 2. 7v, fast - fast process e. the ratio of pullup slew rate to pulldown slew rate is s pecified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the ma ximum difference between pullup and pulldown drivers due to process variation. f. verified under typical condi tions for qualification purposes. g. tsopii package divices only. h. a derating factor will be used to in crease tis and tih in the case where t he input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesser of the slew rates detemined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), si milarly for rising transitions. i. a derating factor will be used to increas e tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise, fall rate and dc-dc del ta rise, input slew rate is based on the lesser of the slew rates determined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps.
ddr sdram ddr sdram 256mb e-die (x4, x8) rev. 1.1 september. 2003 j. table 3 is used to increase tds and tdh in the case where the i/o slew rate is bel ow 0.5 v/ns. the i/o slew rate is based on the lesser on the lesser of the ac - ac slew rate and the dc- dc slew rate. the inut slew rate is based on the lesser of the slew rate s deter mined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), and similarly for rising transitions. k. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotony.

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